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1/26 ? semiconductor msm54v32126a description the msm54v32126a is a graphics dram organized in a 131,072-word 32-bit configuration. the technology used to fabricate the msm54v32126a is oki's cmos silicon gate process technology. the device operates with a single 3.3 v power supply. features ? 131,072-word 32-bit organization ? single 3.3 v power supply, 0.3 v tolerance ? refresh: 512 cycles/8 ms ? fast page mode with extended data out (edo) ? byte write, byte read ? ras only refresh ? cas before ras refresh ? cas before ras self-refresh ? hidden refresh ? package options: 64-pin 525 mil plastic ssop (ssop64-p-525-0.80-k) (product : msm54v32126a-xxgs-k) 70/64-pin 400 mil plastic tsop (type ii)(tsopii70/64-p-400-0.65-k) (product : msm54v32126a-xxts-k) xx indicates speed rank. product family ? semiconductor msm54v32126a 131,072-word 32-bit dynamic ram : fast page mode type with edo preliminary family t rac 50 ns 60 ns operating (max.) 504 mw 486 mw power dissipation cycle time (min.) 100 ns 120 ns msm54v32126a-50 msm54v32126a-60 t aa 25 ns 30 ns t cac 15 ns 18 ns standby (max.) access time (max.) 3.1 mw t oea 15 ns 18 ns 45 ns 540 mw 90 ns msm54v32126a-45 23 ns 13 ns 13 ns e2l0053-17-y1 this version: jan. 1998
2/26 ? semiconductor msm54v32126a pin configuration (top view) pin name function a0 - a8 address input power supply (3.3 v) ground (0 v) nc no connection v cc v ss dq0 - dq31 data input / data output ras row address strobe cas1 - cas4 column address strobe write enable we oe output enable note: the same power supply voltage must be provided to every v cc pin, and the same gnd voltage level must be provided to every v ss pin. 64-pin plastic ssop 70/64-pin plastic tsop ( ii ) ( k t yp e ) dq28 dq29 dq27 v cc dq26 dq24 dq25 dq23 v ss dq22 dq20 dq21 dq19 v cc dq18 dq16 dq17 v ss nc dq14 dq15 nc v cc dq12 dq10 dq11 dq1 dq2 dq3 v cc dq4 dq5 dq6 dq7 dq13 v ss dq30 v cc v ss dq8 dq9 dq31 dq0 a2 a3 v cc cas1 cas2 cas3 cas4 oe a8 a7 a6 a5 a4 v ss v ss nc we a1 a0 nc ras 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 dq28 dq29 dq27 v cc dq26 dq24 dq25 dq23 v ss dq22 dq20 dq21 dq19 v cc dq18 dq16 dq17 v ss nc dq14 dq15 nc v cc dq12 dq10 dq11 dq1 dq2 dq3 v cc dq4 dq5 dq6 dq7 dq13 v ss dq30 v cc v ss dq8 dq9 dq31 dq0 a2 a3 v cc cas1 cas2 cas3 cas4 oe a8 a7 a6 a5 a4 v ss v ss nc we a1 a0 nc ras 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36
3/26 ? semiconductor msm54v32126a block diagram ras cas4 cas3 a0 - a8 we oe dq8 - dq15 dq16 - dq23 v cc v ss dq0 - dq7 dq24 - dq31 cas2 cas1 timing generator refresh control clock column address buffers internal address counter row address buffers row deco- ders word drivers memory cells sense amps column decoders 8 8 99 i/o controller i/o controller 32 i/o selector input buffers output buffers output buffers input buffers 32 8 8 8 8 8 8 8 8 on-chip v bb generator input buffers output buffers output buffers input buffers 8 8 8 8 8 8 8 8 i/o controller i/o controller
4/26 ? semiconductor msm54v32126a electrical characteristics absolute maximum ratings rating C0.5 to 4.5 50 1 0 to 70 C55 to 150 v ma w c c voltage on any pin relative to v ss short circuit output current power dissipation operating temperature storage temperature v t i os p d t opr t stg parameter unit symbol recommended operating conditions input high voltage power supply voltage input low voltage v cc v ss v ih v il max. 3.6 0 3.6 0.3 v v v v typ. 3.3 0 min. 3.0 0 3.0 C0.3 (ta = 0c to 70c) parameter unit symbol capacitance input capacitance c in c io pf pf input / output capacitance max. 7 7 typ. (v cc = 3.3 v 0.3 v, ta = 25c, f = 1 mhz) parameter unit symbol
5/26 ? semiconductor msm54v32126a dc characteristics average power supply current ( cas before ras refresh) ras = cycling, cas before ras 1, 2, 4 ma 110 130 i cc5 average power supply current (fast page mode) ras = v il , cas cycling, t hpc = min. 1, 2, 4 135 140 i cc4 ma input leakage current output high voltage condition note average power supply current (operating) power supply current (standby) output low voltage output leakage current unit average power supply current ( ras only refresh) parameter i oh = C0.1 ma i ol = 0.1 ma 0 v < v in < v cc ; all other pins not under test = 0 v 0 v < v out < 3.6 v output disable ras , cas cycling, t rc = min. ras 3 v cc C 0.2 v, cas 3 v cc C 0.2 v ras = cycling, cas = v ih , t rc = min. v v m a m a 1, 2, 3 ma m a 1, 2, 3 ma max. v cc 0.8 10 10 110 850 110 min. 2.0 0 C10 C10 max. v cc 0.8 10 10 130 850 130 min. 2.0 0 C10 C10 symbol v oh v ol i li i lo i cc1 i cc2 i cc3 msm54v32126a -60 msm54v32126a -50 (v cc = 3.3 v 0.3 v, ta = 0c to 70c) 140 150 max. v cc 0.8 10 10 140 850 140 min. 2.0 0 C10 C10 msm54v32126a -45 average power supply current ( cas before ras self-refresh) ras = v il , cas = v il 1, 2 m a 950 950 i ccs 950 notes: 1. specified values are obtained with minimum cycle time. 2. i cc is dependent on output loading. specified values are obtained with the output open. 3. address can be changed once or less while ras = v il . 4. address can be changed once or less while cas = v ih .
6/26 ? semiconductor msm54v32126a ac characteristics (1/2) parameter symbol note unit t rc t prwc t aa t cac t cpa t rasp t cas t rcd max. min. max. min. msm54v32126a -60 msm54v32126a -50 t hpc t rac t rez t rsh t csh t t t rp t ras t rad t asr t rah t asc t cah t ar t rcs t rch t rrh t wcs t wch t rwc t ral t crp t cp access time from column address column address hold time referenced to ras column address set-up time row address set-up time access time from cas column address hold time cas pulse width cas precharge time (hyper page mode) access time from cas precharge cas to ras precharge time cas hold time output buffer turn-off delay time from ras fast page mode cycle time fast page mode read-modify-write cycle time row address hold time ras pulse width (hyper page mode only) random read or write cycle time ras to cas delay time read command hold time read command set-up time read modify write cycle ras precharge time read command hold time referenced to ras access time from ras ras to column address delay time column address to ras lead time ras pulse width ras hold time transition time (rise and fall) write command set-up time write command hold time ns 120 100 ns 30 25 ns 18 15 ns 35 30 ns 35 3 35 3 ns 100k 60 100k 50 ns 80 70 ns 10k 9 10k 7 9 20 20 ns 24 20 ns 60 50 5 ns 20 3 20 3 ns 54 44 ns 14 14 ns 60 50 ns 10k 60 10k 50 10 15 15 0 0 9 7 0 0 10 8 40 35 0 0 6, 12 0 0 6 0 0 0 0 10 8 4, 10 4, 9 4, 13 4, 9,10 3 ns 42 35 ns 30 25 ns ns ns ns ns ns ns ns ns ns ns 170 145 ns 28 24 8 6 9 7 ns ns 8, 12 t cez output buffer turn-off delay time from cas 5 ns 20 3 20 3 t crl cas "h" to ras "h" lead time 0 0ns t rcl ras "h" to cas "h" lead time 0 0ns t doh data output hold after cas low 11 3 3ns msm54v32126a -45 max. 23 13 28 35 100k 10k 45 20 10k 32 22 20 min. 90 3 45 65 6 20 18 3 39 12 45 45 15 0 6 0 7 30 0 0 0 0 7 135 22 6 6 3 0 0 3 (v cc = 3.3 v 0.3 v, ta = 0c to 70c) note 1, 2, 3 13 15 12 12 12 12
7/26 ? semiconductor msm54v32126a ac characteristics (2/2) parameter symbol note unit t ds t rwd t cwd t dzc t dzo t csr t ref t rass max. min. max. min. msm54v32126a -60 msm54v32126a -50 t dhr t awd t oea t chr t rpc t oez t oeh t roh t rps t chs t dh column address to we delay time cas hold time for cas before ras cycle cas set-up time for cas before ras cycle cas to we delay time data hold time data hold time referenced to ras data set-up time data to cas delay time data to oe delay time cas h old time ( cas before ras self-refresh) oe command hold time refresh period ras hold time referenced to oe ras precharge to cas active time ras to we delay time ras precharge time ( cas before ras self-refresh) access time from oe ras pulse width ( cas before ras self-refresh) output buffer turn-off delay time from oe ns 0 0 ns 40 35 ns 0 0 ns 0 0 ns 20 3 20 3 ns 10 8 ns 80 70 ms 8 8 100 100 ns 40 35 ns 50 45 ns 18 15 ns 10 9 ns 10 8 ns 10 10 ns 12 10 130 110 0 0 8 8 m s ns ns ns 10 8 7, 12 7, 12 8 t wcr t wp t rwl t cwl write command to cas lead time write command to ras lead time write command hold time referenced to ras write command pulse width 40 35 10 9 10 9 10 9 ns ns ns ns t wez output buffer turn-off delay time from we 3 3ns 20 20 5 5 t och oe "l" to cas "h" lead time ns 10 10 t cho cas "h" to oe "l" lead time ns 10 10 t oep oe precharge time ns 12 10 t oed oe to data-in delay time ns 12 12 t cpt cas precharge time (refresh counter test) ns 30 25 msm54v32126a -45 max. min. 0 32 0 0 20 3 6 65 8 100 30 42 13 8 6 10 10 100 0 7 30 8 8 8 320 10 10 10 12 20 t wpe we pulse width (output disable) ns 12 10 10 14 15 12 13 12 (v cc = 3.3 v 0.3 v, ta = 0c to 70c) note 1, 2, 3
8/26 ? semiconductor msm54v32126a notes: 1. an initial pause of 200 m s is required after power-up followed by any 8 ras cycles (example : ras only refresh) before proper device operation is achieved. in case of using internal refresh counter, a minimum of 8 cas before ras cycles instead of 8 ras cycles are required. 2. the ac characteristics assume at t t = 3 ns. 3. v ih (min.) and v il (max.) are reference levels for measuring timing of input signals. also, transition times are measured between v ih and v il . input levels at the ac testing are 3.0 v/0 v. 4. data outputs are measured with a load of 30 pf. dout reference levels : v oh /v ol = 2.0 v/0.8 v. 5. t rez (max.), t cez (max.), t wez (max.) and t oez (max.) define the time at which the outputs achieve the open circuit condition and are not referenced to output voltage levels. this parameter is sampled and not 100% tested. 6. either t rch or t rrh must be satisfied for a read cycle. 7. these parameters are referenced to cas leading edge of early write cycles and to we leading edge in oe controlled write cycles and read modify write cycles. 8. t wcs , t rwd , t cwd and t awd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min.), the cycle is an early write cycle and the data out pin will remain open circuit throughout the entire cycle; if t rwd 3 t rwd (min.), t cwd 3 t cwd (min.) and t awd 3 t awd (min.), the cycle is a read modify write cycle and the data out will contain data read from the selected cell: if neither of the above sets of conditions is satisfied, the condition of the data out is indeterminate. 9. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only: if t rcd is greater than the specified t rcd (max.) limit, then access time is controlled by t cac . 10. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only: if t rad is greater than the specified t rad (max.) limit, then access time is controlled by t aa . 11. this is guaranteed by design. (t doh = t cac - output transition time) this parameter is not 100% tested. 12. these parameters are determined by the earliest falling edge of cas1 , cas2 , cas3 , or cas4 . 13. these parameters are determined by the latest rising edge of cas1 , cas2 , cas3 , or cas4 . 14. t cwl should be satisfied by all cas es. 15. t cp and t cpt are determined by the time that all cas es are high.
9/26 ? semiconductor msm54v32126a casn -dq function table cas1 h h cas2 h h cas3 h h cas4 h l dq0-7 * * dq8-15 * * dq16-23 * * dq24-31 * enable h h l h * * enable * h h l l * * enable enable h l h h * enable * * h l h l * enable * enable h l l h * enable enable * h l l l * enable enable enable l h h h enable * * * l h h l enable * * enable l h l h enable * enable * l h l l enable * enable enable l l h h enable enable * * l l h l enable enable * enable l l l h enable enable enable * llll enable enable enable enable read cycle write cycle enable valid data-out write data * high-z don't care
10/26 ? semiconductor msm54v32126a timing waveform read cycle (outputs controlled by ras ) ras address we dq0 - dq31 cas1 | cas4 "h" or "l" oe t rc t ras t rp t crp t csh t crp t rcd t rsh t cas t rad t asr t rah t asc t cah t ral row column t rcs t rrh t rch t roh t oea t cac t aa t oez t rez open valid data-out t crl t ar t rac
11/26 ? semiconductor msm54v32126a read cycle (outputs controlled by cas ) ras address we dq0 - dq31 cas1 | cas4 "h" or "l" oe t rc t ras t rp t ar t crp t csh t crp t rcd t rsh t cas t rad t asr t rah t asc t cah t ral row column t rcs t rrh t rch t aa t roh t oea t cac t oez t cez open valid data-out t rcl t rac
12/26 ? semiconductor msm54v32126a write cycle (early write) ras cas1 | cas4 address t rc t ras t rp t rcd t cas t rsh t csh t crp t ar t rad t ral row column t rah t asc t cah t asr "h" or "l" we t wp dq0 - dq31 valid data-in t ds t dh oe t rwl t cwl t dhr t wch t wcr t wcs
13/26 ? semiconductor msm54v32126a write cycle ( oe control write) ras cas1 | cas4 address t rc t ras t rp t rcd t cas t rsh t csh t crp t ar t rad t ral row column t rah t asc t cah t asr "h" or "l" we dq0 - dq31 valid data-in t ds t dh oe t rwl t cwl t dhr t wcr t wp t oeh t oed t rcs
14/26 ? semiconductor msm54v32126a read modify write cycle ras cas1 | cas4 address t rwc t ras t rp t rcd t cas t rsh t csh t crp t ar t rad t ral row column t rah t asc t cah t asr "h" or "l" we dq0 - dq31 valid data-in t aa t ds t dh oe t rwl t cwl t rwd t wp t oeh t awd t oea t rac t cac t oed t oez t rcs valid data-out t dzc t dzo t cwd
15/26 ? semiconductor msm54v32126a fast page mode read cycle with edo ras address we dq0 - dq31 cas1 | cas4 oe row column t crp t rp t rasp t cas "h" or "l" column column t rcd t cp t cas t cas t hpc t cah t asc t rad t rcs t rrh t ar t aa valid data-out t rah t asr t cah t asc t cah t asc t rc t csh t crp t cp t rsh t ral t rch t rcs t rch t rcs t rch t cac open t rac valid data-out t oea t cac t cac t rez t doh t doh t oez t aa t aa t cpa t cpa valid data-out
16/26 ? semiconductor msm54v32126a fast page mode write cycle (early write) ras address we dq0 - dq31 cas1 | cas4 oe "h" or "l" t asr row column column column t rah t asc t rad t cah t asc t cah t cah t asc t crp t rcd t cas t ar t rp t rasp t rc t csh t hpc t rsh t crp t cas t cas t cp t ral t cwl t wcs t wp t wch t cwl t wcs t wp t wch t cwl t wcs t wp t wch t rwl t wcr valid data-in t ds t dh valid data-in t ds t dh valid data-in t ds t dh t cp t dhr
17/26 ? semiconductor msm54v32126a fast page mode read modify write cycle ras address we dq0 - dq31 cas1 | cas4 oe "h" or "l" t asr row column column column t rah t asc t rad t cah t asc t cah t cah t asc t crp t rcd t cas t ar t rp t rasp t rc t csh t prwc t rsh t crp t cas t cas t cp t ral t cwd t rcs t cwd t rwd t cp t awd t wp t cwl t awd t cwl t wp t cwd t rwl t cwl t wp t oea t oea t awd t oea t oeh t aa t oez t oed valid data-out t rac t cac t dh t ds t aa t oez t oed valid data-out t dh t ds t cac valid data-out t cac t aa t ds t dh t oez t oed valid data-in valid data-in valid data-in t roh
18/26 ? semiconductor msm54v32126a ras only refresh cycle ras address cas1 | cas4 t crp t rp t ras t rpc row t asr t rah t rc "h" or "l" note: dqs are open, we , oe = "h" or "l"
19/26 ? semiconductor msm54v32126a cas before ras refresh cycle ras casn t rp t ras open t rc t rpc t cp t csr t chr t cez t rp dq0 - dq31 note: we , oe , a0 - a8 = "h" or "l"
20/26 ? semiconductor msm54v32126a hidden refresh read cycle ras cas1 | cas4 address oe "h" or "l" we dq0 - dq31 t rc t rc t ras t rp t ras t rp t ar t crp t rcd t rsh t chr t rad t asr t rah t asc t cah row column t rcs t ral t rrh t aa t roh t oea t cac t rac t oez valid data-out t rez
21/26 ? semiconductor msm54v32126a hidden refresh write cycle ras address we dq0 - dq31 cas1 | cas4 oe "h" or "l" t asr row column t crp t rc t asc t rp t ras t rcd t rsh t rad t cah t rah t ral t rwl t chr t ras t rc t rp t ar t wp t wch t wcr t wcs valid data-in t dhr t dh t ds
22/26 ? semiconductor msm54v32126a ras address we dq0 - dq31 cas1 | cas4 oe t ras t asc t cpt t rsh t cah t cas "h" or "l" t wp t cwl t rp valid data-out open t aa t cez t cac open t rcs t rwl valid data-out t rcs t awd t cwd t rwl t wp t cwl t cac t oez t chr t csr column t rch t rrh t oez t oea t roh t wch t wcs t dh valid data-in t ds t dh t oed t oea t ds valid data-in read cycle write cycle we oe dq0 - dq31 read modify write cycle we oe dq0 - dq31 open t aa t aa t ral cas before ras refresh counter test cycle
23/26 ? semiconductor msm54v32126a cas before ras self-refresh cycle ras casn "h" or "l" t rass t rpc open t rps t rpc t cp t csr t chs t rp dq0 - dq31 t cez note: we , oe , a0 - a8 = "h" or "l"
24/26 ? semiconductor msm54v32126a "h" or "l" t ar ras cas1 | cas4 address row column column column t rasp t rc t rp t crp t rcd t csh t cas t hpc t cp t cas t cp t cas t cp t cas t rsh t crp t asr t rah t asc t rad t cah t asc t cah t asc t cah column t asc t cah t ral we t rcs t rrh t rch t rch t wpe oe t oea t rac t cac t aa t cho t oep t och t oep dq0 - dq31 t aa t cac t doh t cpa valid data-out valid data-out t oez t oea valid* data-out t aa t cac t oez valid* data-out t wez t oea t aa t cac valid data-out t rez * : same data open t rcs fast page mode read with edo high-z operation
25/26 ? semiconductor msm54v32126a (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). ssop64-p-525-0.80-k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 1.34 typ. mirror finish
26/26 ? semiconductor msm54v32126a (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). tsop ii 70/64-p-400-0.65-k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.59 typ. mirror finish

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